As semiconductor devices, including logic devices and memory devices, such as dynamic random-access memory (DRAM) devices, scale to smaller dimensions, device patterning increasingly limits the ability to harness the improvements potentially resulting from smaller size. For example, in present day DRAM devices, known architectures include so-called 8F2 structure and 6F2 structure (architecture) among others. While 6F2 architecture provides a higher device density and greater speed than 8F2 architecture, the ability to form memory devices having appropriate properties is compromised, in part because of patterning problems, such as overlay. As an example, as DRAM cell size shrinks, the 6F2 architecture causes difficulty in forming electrical contact between an access transistor and structures lying above the access transistor, such as a bit line or a storage node capacitor. For example, the storage node capacitor may be formed at a much higher level than the level containing the access transistor. To form an electrical connection between the storage capacitor and access transistor, a structure such as a via may need to be formed, where the via traverses multiple levels including the bit line level and bit line contact level. Because of crowding between bit lines, word lines, and active area forming the access transistors, the contact via may be unable to properly contact the active area of the transistor. For example, to avoid overlapping with a bit line, the contact via may be placed in a position where overlay between the contact via and the storage capacitor, as well as overlay between the contact via and active area of the access transistor may be less than ideal.
With respect to these and other considerations, the present disclosure is provided.